AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 91

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

ARM Request (16-bit)
Read Operations
Figure 32. Code Read Optimization in Thumb Mode for FWS = 0
Note:
6071A–ATARM–28-Oct-04
Data To ARM
Buffer (32 bits)
Flash Access
Master Clock
Code Fetch
When FWS is equal to 0, all accesses are performed in a single-cycle access.
@Byte 0
Bytes 0-3
An optimized controller manages embedded Flash reads. A system of 2 x 32-bit buffers is
added in order to start access at following address during the second read, thus increasing
performance when the processor is running in Thumb mode (16-bit instruction set). See Fig-
ure 32, Figure 33 and Figure 34.
This optimization concerns only Code Fetch and not Data.
The read operations can be performed with or without wait state. Up to 3 wait states can be
programmed in the field FWS (Flash Wait State) in the Flash Mode Register MC_FMR (see
“MC Flash Mode Register” on page 99). Defining FWS to be 0 enables the single-cycle access
of the embedded Flash.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the internal memory
area, the embedded Flash wraps around the address space and appears to be repeated
within it.
@Byte 2
Bytes 0-1
Bytes 4-7
@Byte 4
Bytes 0-3
Bytes 2-3
Bytes 4-5
@Byte 6
Bytes 4-7
Bytes 8-11
@Byte 8
Bytes 6-7
AT91SAM7S32 Preliminary
@Byte 10
Bytes 8-9
Bytes 8-11
Bytes 12-15
Bytes 10-11
@Byte 12
Bytes 12-13
@Byte 14
Bytes 12-15
Bytes 16-19
Bytes 14-15
@Byte 16
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