AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 48

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Watchdog Reset
Figure 20. Watchdog Reset
48
AT91SAM7S32 Preliminary
WDRPROC = 0
Only if
periph_nreset
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock
cycles.
When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in
WDT_MR:
•
•
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes
a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog
Reset, and the Watchdog is enabled by default and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset
controller.
proc_nreset
(nrst_out)
RSTTYP
wd_fault
If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The
NRST line is also asserted, depending on the programming of the field ERSTL. However,
the resulting low level on NRST does not result in a User Reset state.
If WDRPROC = 1, only the processor reset is asserted.
NRST
SLCK
MCK
Freq.
Any
Any
Processor Startup
= 3 cycles
XXX
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
0x2 = Watchdog Reset
6071A–ATARM–28-Oct-04