AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 92

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 33. Code Read Optimization in Thumb Mode for FWS = 1
Note:
Figure 34. Code Read Optimization in Thumb Mode for FWS = 3
Note:
92
ARM Request (16-bit)
ARM Request (16-bit)
Data To ARM
Buffer (32 bits)
Buffer (32 bits)
Flash Access
Flash Access
Data To ARM
Master Clock
Master Clock
When FWS is equal to 1, in case of sequential reads, all the accesses are performed in a single-cycle access (except for the
first one).
When FWS is equal to 2 or 3, in case of sequential reads, the first access takes FWS cycles, the second access one cycle, the
third access FWS cycles, the fourth access one cycle, etc.
Code Fetch
Code Fetch
AT91SAM7S32 Preliminary
@Byte 0
@Byte 0
1 Wait State Cycle
3 Wait State Cycles
Bytes 0-3
Bytes 0-3
@Byte 2
Bytes 0-1
@2
0-1
1 Wait State Cycle
3 Wait State Cycles
@4
2-3
@Byte 4
Bytes 2-3
Bytes 0-3
Bytes 4-7
Bytes 4-7
Bytes 0-3
@Byte 6
Bytes 4-5
@6
4-5
1 Wait State Cycle
3 Wait State Cycles
@8
6-7
@Byte 8
Bytes 6-7
Bytes 8-11
Bytes 4-7
Bytes 8-11
Bytes 4-7
@Byte 10
Bytes 8-9
@10
8-9 10-11
1 Wait State Cycle
3 Wait State Cycles
@12
Bytes 10-11
@Byte 12
Bytes 12-15
6071A–ATARM–28-Oct-04
Bytes 12-15
Bytes 8-11
Bytes 8-11
Bytes 12-13
@Byte 14
12-13