AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 276

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Synchronous Receiver
Receiver Operations
Figure 109. Receiver Status
276
Baud Rate
US_RHR
AT91SAM7S32 Preliminary
RXRDY
US_CR
OVRE
Clock
Write
Read
RXD
Start
Bit
D0
In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of
the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the par-
ity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous
mode operations provide a high speed transfer capability.
Configuration fields and bits are the same as in asynchronous mode.
Figure 108 illustrates a character reception in synchronous mode.
Figure 108. Synchronous Mode Character Reception
When a character reception is completed, it is transferred to the Receive Holding Register
(US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is com-
pleted while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is
transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing
the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1.
D1
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
D2
Sampling
D3
Clock
RXD
D4
D5
D6
Start
D7
Parity
Bit
D0
Stop
Bit
Start
Bit
D1
D0
D1
D2
D2
D3
D3
D4
D5
D4
D6
D7
D5
Parity
Bit
Stop
Bit
D6
RSTSTA = 1
D7
6071A–ATARM–28-Oct-04
Parity Bit
Stop Bit