AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 234

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

234
AT91SAM7S32 Preliminary
The bits are shifted out on the MISO line and sampled on the MOSI line.
When all the bits are processed, the received data is transferred in the Receive Data Register
and the RDRF bit rises. If RDRF is already high when the data is transferred, the Overrun bit
rises and the data transfer to SPI_RDR is aborted.
When a transfer starts, the data shifted out is the data present in the Shift Register. If no data
has been written in the Transmit Data Register (SPI_TDR), the last data received is trans-
ferred. If no data has been received since the last reset, all bits are transmitted low, as the
Shift Register resets at 0.
When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and
the TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e.
NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data
written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables
frequent updates of critical variables with single transfers.
Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no
character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the
last load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last
received character is retransmitted.
Figure 88 shows a block diagram of the SPI when operating in Slave Mode.
Figure 88. Slave Mode Functional Block Diagram
SPCK
MOSI
NSS
SPIDIS
SPIEN
SPIENS
SPI_CSR0
LSB
NCPHA
CPOL
BITS
FLOAD
Shift Register
Clock
SPI
SPI_RDR
SPI_TDR
RD
TD
MSB
OVRES
RDRF
TDRE
6071A–ATARM–28-Oct-04
MISO