AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 278

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Multi-drop Mode
Transmitter Timeguard
Figure 111. Timeguard Operations
278
Baud Rate
TXEMPTY
US_THR
TXRDY
Clock
Write
TXD
AT91SAM7S32 Preliminary
Start
Bit
D0
D1
D2
If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x7, the
USART runs in Multi-drop mode. This mode differentiates the data characters and the address
characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the
parity bit at 1.
If the USART is configured in multi-drop mode, the receiver sets the PARE parity error bit
when the parity bit is high and the transmitter is able to send a character with the parity bit high
when the Control Register is written with the SENDA bit at 1.
To handle parity error, the PARE bit is cleared when the Control Register is written with the bit
RSTSTA at 1.
The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In
this case, the next byte written to US_THR is transmitted as an address. Any character written
in US_THR without having written the command SENDA is transmitted normally with the parity
at 0.
The timeguard feature enables the USART interface with slow remote devices.
The timeguard function enables the transmitter to insert an idle state on the TXD line between
two characters. This idle state actually acts as a long stop bit.
The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Reg-
ister (US_TTGR). When this field is programmed at zero no timeguard is generated.
Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the
number of bit periods programmed in TG in addition to the number of stop bits.
As illustrated in Figure 111, the behavior of TXRDY and TXEMPTY status bits is modified by
the programming of a timeguard. TXRDY rises only when the start bit of the next character is
sent, and thus remains at 0 during the timeguard transmission if a character has been written
in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the time-
guard is part of the current character being transmitted.
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
TG = 4
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
6071A–ATARM–28-Oct-04
TG = 4