AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 203

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Input Glitch
Filtering
Figure 78. Input Glitch Filter Timing
Input Change
Interrupt
6071A–ATARM–28-Oct-04
if PIO_IFSR = 0
if PIO_IFSR = 1
PIO_PDSR
PIO_PDSR
Pin Level
MCK
1 cycle
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise
PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
Optional input glitch filters are independently programmable on each I/O line. When the glitch
filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automat-
ically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For
pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or
may not be taken into account, depending on the precise timing of its occurrence. Thus for a
pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably fil-
tered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one
Master Clock cycle latency if the pin level change occurs before a rising edge. However, this
latency does not appear if the pin level change occurs before a falling edge. This is illustrated
in Figure 78.
The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register),
PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing
PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register
enables the glitch filter on the I/O lines.
When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripher-
als. It acts only on the value read in PIO_PDSR and on the input change interrupt detection.
The glitch filters require that the PIO Controller clock is enabled.
The PIO Controller can be programmed to generate an interrupt when it detects an input
change on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt
Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and
disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR
(Interrupt Mask Register). As Input change detection is possible only by comparing two suc-
cessive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The
Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. config-
ured as an input only, controlled by the PIO Controller or assigned to a peripheral function.
When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt
Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt
line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to
generate a single interrupt signal to the Advanced Interrupt Controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies
that all the interrupts that are pending when PIO_ISR is read must be handled.
1 cycle
up to 1.5 cycles
AT91SAM7S32 Preliminary
1 cycle
up to 2.5 cycles
2 cycles
up to 2 cycles
1 cycle
1 cycle
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