AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 387

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AT91SAM7S32-AI

Manufacturer Part Number
AT91SAM7S32-AI
Description
AT91 ARM Thumb-based Microcontrollers
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
PWM Channel Counter Register
Register Name: PWM_CCNTx
Access Type:
• CNT: Channel Counter Register
Internal counter value. This register is reset when:
PWM Channel Update Register
Register Name: PWM_CUPDx
Access Type:
This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modify-
ing the waveform period or duty-cycle.
Only the first 16 bits (internal channel counter size) are significative.
6071A–ATARM–28-Oct-04
CPD (PWM_CMRx Register)
the channel is enabled (writing CHIDx in the PWM_ENA register).
the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned.
31
23
15
31
23
15
7
7
0
1
Read-only
Write-only
30
22
14
30
22
14
6
6
The duty-cycle (CDTC in the PWM_CDRx register) is updated with the CUPD value at the
beginning of the next period.
The period (CPRD in the PWM_CPRx register) is updated with the CUPD value at the beginning
of the next period.
29
21
13
29
21
13
5
5
28
20
12
28
20
12
4
4
CUPD
CUPD
CUPD
CUPD
CNT
CNT
CNT
CNT
27
19
27
19
11
11
3
3
AT91SAM7S32 Preliminary
26
18
10
26
18
10
2
2
25
17
25
17
9
1
9
1
24
16
24
16
8
0
8
0
387

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