AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 81
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AT91SAM7S32-AI
Manufacturer Part Number
AT91SAM7S32-AI
Description
AT91 ARM Thumb-based Microcontrollers
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT91SAM7S32-AI.pdf
(446 pages)
- Current page: 81 of 446
- Download datasheet (3Mb)
Memory Controller (MC)
Overview
Block Diagram
Figure 28. Memory Controller Block Diagram
6071A–ATARM–28-Oct-04
ARM7TDMI
Peripheral
Processor
Controller
Data
The Memory Controller (MC) manages the ASB bus and controls accesses requested by the
masters, typically the ARM7TDMI processor and the Peripheral Data Controller. It features a
simple bus arbiter, an address decoder, an abort status, a misalignment detector and an
Embedded Flash Controller.
Abort
Peripheral N
Peripheral 0
Peripheral 1
Memory Controller
Arbiter
Bus
ASB
Misalignment
Interface
Detector
Status
Abort
User
AT91SAM7S32 Preliminary
Bridge
APB
APB
Address
Decoder
Embedded
Controller
Flash
From Master
to Slave
Internal
Internal
Flash
RAM
81
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