HD6433682 ETC, HD6433682 Datasheet - Page 106

• Manufacturer Part Number: HD6433682
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
• Manufacturer: ETC

6.1.1
SYSCR1 controls the power-down modes, as well as SYSCR2.
Rev. 3.00, 05/03, page 76 of 472
Bit
7
6
5
4
3
2 to 0
Bit Name
SSBY
STS2
STS1
STS0
NESEL
System Control Register 1 (SYSCR1)
Initial
Value
0
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Software Standby
This bit selects the mode to transit after the execution of
the SLEEP instruction.
0: Enters sleep mode or subsleep mode.
1: Enters standby mode.
For details, see table 6.2.
Standby Timer Select 2 to 0
These bits designate the time the CPU and peripheral
modules wait for stable clock operation after exiting from
standby mode, subactive mode, or subsleep mode to
active mode or sleep mode due to an interrupt. The
designation should be made according to the clock
frequency so that the waiting time is at least 6.5 ms. The
relationship between the specified value and the number
of wait states is shown in table 6.1. When an external
clock is to be used, the minimum value (STS2 = STS1 =
STS0 =1) is recommended.
Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch clock
signal (
generates the oscillator clock (
sampling frequency of the oscillator clock when the watch
clock signal (
clear NESEL to 0.
0: Sampling rate is
1: Sampling rate is
Reserved
These bits are always read as 0.
W
) and the system clock pulse generator
W
) is sampled. When
OSC
OSC
/16
/4
OSC
). This bit selects the
OSC
=2 to 10 MHz,