HD6433682 ETC, HD6433682 Datasheet - Page 214

• Manufacturer Part Number: HD6433682
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
• Manufacturer: ETC

Notes: 1. When GR functions as an output compare register, TCNT is cleared by compare match.
13.3.10 Timer I/O Control Register (TIORA and TIORC)
The TIOR registers control the general registers (GR). Timer Z has four TIOR registers
(TIORA_0, TIORA_1, TIORC_0, and TIORC_1), two for each channel. In PWM mode including
complementary PWM mode and reset synchronous PWM mode, the settings of TIOR are invalid.
TIORA: TIORA selects whether GRA or GRB is used as an output compare register or an input
capture register. When an output compare register is selected, the output setting is selected. When
an input capture register is selected, an input edge of an input capture signal is selected. TIORA
also selects the function of FTIOA or FTIOB pin.
Rev. 3.00, 05/03, page 184 of 472
Bit
2
1
0
Bit
7
6
5
4
2. Synchronous operation is set by TMDR.
3. X: Don’t care
Bit Name
TPSC2
TPSC1
TPSC0
Bit Name
IOB2
IOB1
IOB0
When GR functions as input capture, TCNT is cleared by input capture.
Initial
value
0
0
0
Initial
value
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Time Prescaler 2 to 0
000: Internal clock: count by
001: Internal clock: count by /2
010: Internal clock: count by /4
011: Internal clock: count by /8
1XX: External clock: count by FTIOA0 (TCLK) pin input
Description
Reserved
This bit is always read as 1.
I/O Control B2 to B0
GRB is an output compare register:
000: Disables pin output by compare match
001: 0 output by GRB compare match
010: 1 output by GRB compare match
011: Toggle output by GRB compare match
GRB is an input capture register:
100: Input capture to GRB at the rising edge
101: Input capture to GRB at the falling edge
11X: Input capture to GRB at both rising and falling edges