HD6433682 ETC, HD6433682 Datasheet - Page 340

• Manufacturer Part Number: HD6433682
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
• Manufacturer: ETC

17.4.7
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 17.16 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Rev. 3.00, 05/03, page 310 of 472
processing
ICDRR
ICDRS
(Input)
RDRF
MST
SCL
TRS
SDA
User
SCL or SDA
input signal
Sampling
clock
Noise Canceler
[2] Set MST
(when outputting the clock)
Bit 0
Figure 17.16 Block Diagram of Noise Conceler
1
Figure 17.15 Receive Mode Operation Timing
Sampling clock
D
System clock
Data 1
period
Latch
Bit 1
C
2
Q
Bit 6
D
7
Latch
[3] Read ICDRR
C
Bit 7
8
Q
Bit 0
Data 2
1
Data 1
March detector
Bit 6
7
Bit 7
8
SCL or SDA
Internal
signal
1
[3] Read ICDRR
Data 2
Data 3
Bit 0
2