HD6433682 ETC, HD6433682 Datasheet - Page 95

• Manufacturer Part Number: HD6433682
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
• Manufacturer: ETC

Table 4.1
4.1.2
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
4.1.3
BARH and BARL are 16-bit read/write registers that set the address for generating an address
break interrupt. When setting the address break condition to the instruction execution cycle, set
the first byte address of the instruction. The initial value of this register is H'FFFF.
4.1.4
BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break
interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8-
bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for
even and odd addresses in the data transmission. Therefore, comparison data must be set in
ROM space
RAM space
I/O register with 8-bit data
bus width
I/O register with 16-bit data
bus width
Bit
7
6
5 to 0
Bit Name
ABIF
ABIE
Address Break Status Register (ABRKSR)
Break Address Registers (BARH, BARL)
Break Data Registers (BDRH, BDRL)
Access and Data Bus Used
Initial
Value
All 1
0
0
Upper 8 bits
Upper 8 bits
Even Address Odd Address
Upper 8 bits
Upper 8 bits
R/W
R/W
R/W
Word Access
Description
[Setting condition]
When the condition set in ABRKCR is satisfied
[Clearing condition]
When 0 is written after ABIF=1 is read
When this bit is 1, an address break interrupt request is
enabled.
Reserved
These bits are always read as 1.
Address Break Interrupt Flag
Address Break Interrupt Enable
Lower 8 bits
Lower 8 bits
Upper 8 bits
Lower 8 bits
Upper 8 bits
Upper 8 bits
Even Address Odd Address
Upper 8 bits
Rev. 3.00, 05/03, page 65 of 472
Byte Access
Upper 8 bits
Upper 8 bits
Upper 8 bits