HD6433682 ETC, HD6433682 Datasheet - Page 216

• Manufacturer Part Number: HD6433682
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
• Manufacturer: ETC

Legend: X: Don't care
13.3.11 Timer Status Register (TSR)
TSR indicates generation of an overflow/underflow of TCNT and a compare match/input capture
of GRA, GRB, GRC, and GRD. These flags are interrupt sources. If an interrupt is enabled by a
corresponding bit in TIER, TSR requests an interrupt for the CPU. Timer Z has two TSR registers,
one for each channel.
Rev. 3.00, 05/03, page 186 of 472
Bit
3
2
1
0
Bit
7, 6
5
4
Bit Name
IOC2
IOC1
IOC0
Bit Name
UDF*
OVF
Initial
value
1
0
0
0
Initial
value
All 1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
This bit is always read as 1.
I/O Control C2 to C0
GRC is an output compare register:
000: Disables pin output by compare match
001: 0 output by GRC compare match
010: 1 output by GRC compare match
011: Toggle Output by GRC compare match
GRC is an input capture register:
100: Input capture to GRC at the rising edge
101: Input capture to GRC at the falling edge
11X: Input capture to GRC at both rising and falling
Description
Reserved
These bits are always read as 1.
Underflow Flag
[Setting condition]
[Clearing condition]
Overflow Flag
[Setting condition]
[Clearing condition]
When TCNT_1 underflows
When 0 is written to UDF after reading UDF = 1
When the TCNT value underflows
When 0 is written to OVF after reading OVF = 1
edges