HD6433682 ETC, HD6433682 Datasheet - Page 345

• Manufacturer Part Number: HD6433682
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
• Manufacturer: ETC

17.5
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost/overrun error. Table 17.3 shows the
contents of each interrupt request.
Table 17.3 Interrupt Requests
When interrupt conditions described in table 17.3 are 1 and the I bit in CCR is 0, the CPU
executes an interrupt exception processing. Interrupt sources should be cleared in the exception
processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to
ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the
same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive
data of one byte may be transmitted.
Interrupt Request
Transmit Data Empty TXI
Transmit End
Receive Data Full
STOP Recognition
NACK Receive
Arbitration
Lost/Overrun Error
Interrupt Request
Abbreviation Interrupt Condition
TEI
RXI
STPI
NAKI
(TDRE=1) (TIE=1)
(TEND=1) (TEIE=1)
(RDRF=1) (RIE=1)
(STOP=1) (STIE=1)
{(NACKF=1)+(AL=1)}
(NAKIE=1)
I
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Rev. 3.00, 05/03, page 315 of 472
C Mode
Clocked
Synchronous Mode
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