HD6433682 ETC, HD6433682 Datasheet - Page 245

• Manufacturer Part Number: HD6433682
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
• Manufacturer: ETC

settings. Also, the transfer conditions in buffer operation differ from usual settings. Such timings
are shown in figures 13.33 and 13.34.
When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when
the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been
designated for BR, BR is transferred to GR when the counter is incremented by compare match
A0 or when TCNT_1 is underflowed.
TCNT
GRA_0
IMFA
GR
TCNT
Buffer transfer signal
UDF
GR
Buffer transfer signal
Figure 13.34 Timing of Undershooting
Figure 13.33 Timing of Overshooting
H'0001
N-1
Transferred
to buffer
Transferred
to buffer
Set to 1
Set to 1
H'0000
N
N
H'FFFF
Not transferred
to buffer
N+1
Flag is not set
Rev. 3.00, 05/03, page 215 of 472
H'0000
Not transferred
to buffer
Flag is not set
N
H'0001
N-1