HD6433682 ETC, HD6433682 Datasheet - Page 68

• Manufacturer Part Number: HD6433682
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
• Manufacturer: ETC

2.6
CPU operation is synchronized by a system clock ( ) or a subclock (
rising edge of or
states or three states. The cycle differs depending on whether access is to on-chip memory or to
on-chip peripheral modules.
2.6.1
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
Rev. 3.00, 05/03, page 38 of 472
Basic Bus Cycle
Access to On-Chip Memory (RAM, ROM)
ø or ø
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
SUB
SUB
to the next rising edge is called one state. A bus cycle consists of two
Figure 2.9 On-Chip Memory Access Cycle
T
1
state
Bus cycle
Address
Write data
Read data
T
2
state
SUB
). The period from a