HD6433682 ETC, HD6433682 Datasheet - Page 300

• Manufacturer Part Number: HD6433682
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
• Manufacturer: ETC

16.5.4
Figure 16.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In
serial reception, the SCI3 operates as described below.
1.
2.
3.
4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 16.13 shows a sample flow
chart for serial data reception.
Rev. 3.00, 05/03, page 270 of 472
RDRF
OER
LSI
operation
User
processing
Serial
clock
Serial
data
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated.
The SCI3 performs internal initialization synchronous with a synchronization clock input or
output, starts receiving data.
The SCI3 stores the receive data in RSR.
If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
Serial Data Reception (Clocked Synchronous Mode)
Figure 16.12 Example of SCI3 Reception in Clocked Synchronous Mode
RXI interrupt
request
generated
Bit 7
Bit 0
RDRF flag
cleared
to 0
RDR data read
1 frame
Bit 7
RXI interrupt request generated
Bit 0
Bit 1
1 frame
RDR data has
not been read
(RDRF = 1)
Bit 6
Bit 7
ERI interrupt request
generated by
overrun error
Overrun error
processing