HD6433682 ETC, HD6433682 Datasheet - Page 23

• Manufacturer Part Number: HD6433682
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
• Manufacturer: ETC

Figure 16.7 Example of SCI3 Reception in Asynchronous Mode
Figure 16.8 Sample Serial Reception Data Flowchart (Asynchronous Mode)(1).......................265
Figure 16.8 Sample Serial Reception Data Flowchart (Asynchronous Mode)(2).......................266
Figure 16.9 Data Format in Clocked Synchronous Communication ..........................................267
Figure 16.10 Example of SCI3 Transmission in Clocked Synchronous Mode...........................268
Figure 16.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................269
Figure 16.12 Example of SCI3 Reception in Clocked Synchronous Mode ................................270
Figure 16.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)......................271
Figure 16.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Figure 16.15 Example of Inter-Processor Communication Using Multiprocessor Format
Figure 16.16 Sample Multiprocessor Serial Transmission Flowchart ........................................276
Figure 16.17 Sample Multiprocessor Serial Reception Flowchart (1) ........................................278
Figure 16.17 Sample Multiprocessor Serial Reception Flowchart (2) ........................................279
Figure 16.18 Example of SCI3 Reception Using Multiprocessor Format
Figure 16.19 Receive Data Sampling Timing in Asynchronous Mode.......................................283
Section 17 I
Figure 17.1 Block Diagram of I
Figure 17.2 External Circuit Connections of I/O Pins ................................................................287
Figure 17.3 I
Figure 17.4 I
Figure 17.5 Master Transmit Mode Operation Timing (1) .........................................................301
Figure 17.6 Master Transmit Mode Operation Timing (2) .........................................................301
Figure 17.7 Master Receive Mode Operation Timing (1)...........................................................303
Figure 17.8 Master Receive Mode Operation Timing (2)...........................................................303
Figure 17.9 Slave Transmit Mode Operation Timing (1) ...........................................................305
Figure 17.10 Slave Transmit Mode Operation Timing (2) .........................................................306
Figure 17.11 Slave Receive Mode Operation Timing (1) ...........................................................307
Figure 17.12 Slave Receive Mode Operation Timing (2) ...........................................................307
Figure 17.13 Clocked Synchronous Serial Transfer Format.......................................................308
Figure 17.14 Transmit Mode Operation Timing.........................................................................309
Figure 17.15 Receive Mode Operation Timing ..........................................................................310
Figure 17.16 Block Diagram of Noise Conceler.........................................................................310
Figure 17.17 Sample Flowchart for Master Transmit Mode.......................................................311
Figure 17.18 Sample Flowchart for Master Receive Mode ........................................................312
Figure 17.19 Sample Flowchart for Slave Transmit Mode.........................................................313
Figure 17.20 Sample Flowchart for Slave Receive Mode ..........................................................314
Figure 17.21 The Timing of the Bit Synchronous Circuit ..........................................................316
(8-Bit Data, Parity, One Stop Bit)............................................................................264
2
2
2
(Clocked Synchronous Mode) ...............................................................................273
(Transmission of Data H'AA to Receiving Station A) ...........................................275
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ..............................280
C Bus Interface 2 (IIC2)
C Bus Formats ......................................................................................................299
C Bus Timing........................................................................................................299
2
C Bus Interface 2.....................................................................286
Rev. 3.00, 05/03, page xxiii of xxx