S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 107

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S912XET256J2VAGR

Manufacturer Part Number
S912XET256J2VAGR
Description
16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XET256J2VAGR

Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
256 KB
Data Ram Size
16 KB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
24
Interface Type
CAN, SCI, SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V
1. Always “0” on Port A, B, C, D, E, K, AD0, and AD1.
2. Applicable only on Port P, H, and J.
Freescale Semiconductor
DDR
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IO
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
All register bits in this module are completely synchronous to internal
clocks during a register read.
RDR
0
0
1
1
0
0
1
1
x
x
x
x
x
x
x
PE
0
1
1
0
0
1
1
x
x
x
x
x
x
x
x
MC9S12XE-Family Reference Manual Rev. 1.25
Table 2-3. Pin Configuration Summary
PS
x
0
1
0
1
0
1
x
x
x
x
0
1
0
1
(1)
IE
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
(2)
NOTE
Input
Input
Input
Input
Input
Input
Input
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Function
Chapter 2 Port Integration Module (S12XEPIMV1)
Disabled
Pull Up
Pull Down
Disabled
Disabled
Pull Up
Pull Down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Pull Device
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Disabled
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Interrupt
107

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