S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 1158

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2)
29.3.2.7
The FSTAT register reports the operational status of the Flash module.
1. Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
1158
ERSVIE1
ERSVIE0
Offset Module Base + 0x0006
DFDIE
Reset
SFDIE
Field
3
2
1
0
W
R
CCIF
EEE Error Type 1 Interrupt Enable — The ERSVIE1 bit controls interrupt generation when a change state error
is detected during an EEE operation.
0 ERSVIF1 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF1 flag is set (see
EEE Error Type 0 Interrupt Enable — The ERSVIE0 bit controls interrupt generation when a sector format error
is detected during an EEE operation.
0 ERSVIF0 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF0 flag is set (see
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see
1 An interrupt will be requested whenever the SFDIF flag is set (see
Flash Status Register (FSTAT)
1
7
= Unimplemented or Reserved
Table 29-16. FERCNFG Field Descriptions (continued)
0
0
6
Figure 29-11. Flash Status Register (FSTAT)
MC9S12XE-Family Reference Manual Rev. 1.25
ACCERR
0
5
FPVIOL
0
4
Description
MGBUSY
0
3
Section
Section
Section
Section
Section
RSVD
29.3.2.8)
0
2
29.3.2.8)
29.3.2.8)
29.3.2.8)
29.3.2.8)
Freescale Semiconductor
0
1
(1)
MGSTAT[1:0]
Section
0
0
1
29.6).