S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 139

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

1. Read: Anytime.
2.3.47
Freescale Semiconductor
Address 0x025A
Write: Anytime.
DDRP
DDRP
Field
Field
PTIP
Reset
7-0
6-0
7
W
R
Port P input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
Port P data direction—
This register controls the data direction of pin 7.
The enabled PWM channel 7 forces the I/O state to be an output. If the PWM shutdown feature is enabled this pin
is forced to be an input. In these cases the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port P data direction—
The PWM forces the I/O state to be an output for each port line associated with an enabled PWM6-0 channel. In this
case the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
DDRP7
Port P Data Direction Register (DDRP)
0
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTP or PTIP registers, when changing the
DDRP register.
DDRP6
0
6
Figure 2-45. Port P Data Direction Register (DDRP)
Table 2-43. DDRP Register Field Descriptions
Table 2-42. PTIP Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
DDRP5
0
5
DDRP4
NOTE
0
4
Description
Description
DDRP3
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
DDRP2
0
2
Access: User read/write
DDRP1
0
1
DDRP0
0
0
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