S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 252

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 5 External Bus Interface (S12XEBIV4)
5.4.2.4.2
5.4.2.4.3
252
DATA[15:0] (external read)
RW
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (write)
RW
Bus cycle ->
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (write)
RW
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (write)
RW
Write Access Timing
Read-Write-Read Access Timing
Table 5-18. Interleaved Read-Write-Read Accesses (1 Cycle)
...
...
...
...
...
...
...
...
addr 0
high
...
?
1
?
0
MC9S12XE-Family Reference Manual Rev. 1.25
Table 5-14. Read Access (n–1 Cycles)
Table 5-17. Write Access (n–1 Cycles)
...
...
...
...
...
...
Table 5-16. Write Access (2 Cycles)
...
...
...
...
...
...
1
Table 5-15. Write Access (1 Cycle)
iqstat-1
Access #0
acc 0
low
addr 0
addr 0
1
?
0
z
high
high
Access #0
?
0
?
0
1
1
1
addr 0
iqstat -1
high
iqstat-1
acc 0
acc 0
1
0
z
low
low
?
0
Access #0
?
0
Access #0
data 0
2
iqstat 0
000
low
addr 0
addr 1
1
x
0
z
high
high
Access #1
Access #1
1
0
data 0
data 0
2
2
2
addr 0
iqstat 0
iqstat 0
high
acc 1
z
1
0
000
low
low
x
1
x
0
data 1
3
0000
000
low
addr 2
addr 1
z
1
x
0
high
high
Access #2
Access #1
1
1
Access #2
...
...
...
...
...
...
...
...
3
3
Freescale Semiconductor
iqstat 1
data 2
acc 2
acc 1
0000
3
low
low
data 0
addr 1
x
1
x
x
1
high
1
Access #1
1
...
...
...
...
...
...
...
...
...
...
...
...
...
...
n
acc 1
0000
low
...
z
1
x
x
1
...
...
...
...
...
...
...
...
...