S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 816

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S912XET256J2VAGR

Manufacturer Part Number
S912XET256J2VAGR
Description
16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XET256J2VAGR

Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
256 KB
Data Ram Size
16 KB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
24
Interface Type
CAN, SCI, SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V
Chapter 23 Voltage Regulator (S12VREGL3V3V1)
23.1.3
Figure 23-1
REG consists of three parallel subblocks, REG1, REG2 and REG3, providing three independent output
voltages.
816
3. Shutdown mode
Controlled by VREGEN (see device level specification for connectivity of VREGEN).
This mode is characterized by minimum power consumption. The regulator outputs are in a high-
impedance state, only the POR feature is available, LVD, LVR and HTD are disabled. The API
internal RC oscillator clock is not available.
This mode must be used to disable the chip internal regulator VREG_3V3, i.e., to bypass the
VREG_3V3 to use external supplies.
Block Diagram
shows the function principle of VREG_3V3 by means of a block diagram. The regulator core
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor

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