S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 716

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
19.4.2.6
For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the
corresponding PWM output will be center aligned.
The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is
equal to $00. The counter compares to two registers, a duty register and a period register as shown in the
block diagram in
changes state, causing the PWM waveform to also change state. A match between the PWM counter and
the period register changes the counter direction from an up-count to a down-count. When the PWM
counter decrements and matches the duty register again, the output flip-flop changes state causing the
PWM output to also change state. When the PWM counter decrements and reaches zero, the counter
direction changes from a down-count back to an up-count and a load from the double buffer period and
duty registers to the associated registers is performed, as described in
Duty”. The counter counts from 0 up to the value in the period register and then back down to 0. Thus the
effective period is PWMPERx*2.
716
PPOLx = 0
PPOLx = 1
Center Aligned Outputs
Changing the PWM output mode from left aligned to center aligned output
(or vice versa) while channels are operating can cause irregularities in the
PWM output. It is recommended to program the output mode before
enabling the PWM channel.
Figure
E = 100 ns
Figure 19-21. PWM Left Aligned Output Example Waveform
19-19. When the PWM counter matches the duty register, the output flip-flop
Figure 19-22. PWM Center Aligned Output Waveform
PWMDTYx
MC9S12XE-Family Reference Manual Rev. 1.25
PWMPERx
Period = 400 ns
Period = PWMPERx*2
Duty Cycle = 75%
NOTE
PWMPERx
Section 19.4.2.3, “PWM Period and
PWMDTYx
Freescale Semiconductor