S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 753

Manufacturer Part Number

S912XET256J2VAGR

16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI

Manufacturer

Freescale Semiconductor

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Package / Case

Mounting Style

A/d Bit Size

A/d Channels Available

Interface Type

CAN, SCI, SPI

Maximum Operating Temperature

Minimum Operating Temperature

Number Of Programmable I/os

Number Of Timers

Program Memory Type

Supply Voltage - Max

1.98 V, 2.9 V, 5.5 V

Supply Voltage - Min

1.72 V, 2.7 V, 3.13 V

Figure 20-26

after the reset is low but is not preceded by three high samples that would qualify as a falling edge.

Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may

set the framing error ﬂag.

noise ﬂag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are

If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it

sets the framing error ﬂag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE ﬂag

because a break character has no stop bit. The FE ﬂag is set at the same time that the RDRF ﬂag is set.

Freescale Semiconductor

RT Clock Count

Reset RT Clock

20-27, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the

shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample

Framing Errors

MC9S12XE-Family Reference Manual Rev. 1.25

Figure 20-26. Start Bit Search Example 5

Figure 20-27. Start Bit Search Example 6

Chapter 20 Serial Communication Interface (S12SCIV5)

No Start Bit Found