S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 360

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 10 XGATE (S12XGATEV3)
360
XGSWEFM
XGFACTM
XGDBG
XGFRZ
XGIEM
Field
XGE
11
9
8
7
6
5
XGFACT Mask — This bit controls the write access to the XGFACT bit. The XGFACT bit can only be set or
cleared if a "1" is written to the XGFACTM bit in the same register access.
Read:
Write:
0 Disable write access to the XGFACT in the same bus cycle
1 Enable write access to the XGFACT in the same bus cycle
XGSWEF Mask — This bit controls the write access to the XGSWEF bit. The XGSWEF bit can only be cleared
if a "1" is written to the XGSWEFM bit in the same register access.
Read:
Write:
0 Disable write access to the XGSWEF in the same bus cycle
1 Enable write access to the XGSWEF in the same bus cycle
XGIE Mask — This bit controls the write access to the XGIE bit. The XGIE bit can only be set or cleared if a "1"
is written to the XGIEM bit in the same register access.
Read:
Write:
0 Disable write access to the XGIE in the same bus cycle
1 Enable write access to the XGIE in the same bus cycle
XGATE Module Enable (Request Enable)— This bit enables incoming XGATE requests from the S12X_INT
module. If the XGE bit is cleared, pending XGATE requests will be ignored. The thread that is executed by the
RISC core while the XGE bit is cleared will continue to run.
Read:
0 Incoming requests are disabled
1 Incoming requests are enabled
Write:
0 Disable incoming requests
1 Enable incoming requests
Halt XGATE in Freeze Mode — The XGFRZ bit controls the XGATE operation in Freeze Mode (BDM active).
Read:
0 RISC core operates normally in Freeze (BDM active)
1 RISC core stops in Freeze Mode (BDM active)
Write:
0 Don’t stop RISC core in Freeze Mode (BDM active)
1 Stop RISC core in Freeze Mode (BDM active)
XGATE Debug Mode — This bit indicates that the XGATE is in Debug Mode (see
Debug Mode can be entered by Software Breakpoints (BRK instruction), Tagged or Forced Breakpoints (see
S12X_DBG Section), or by writing a "1" to this bit.
Read:
0 RISC core is not in Debug Mode
1 RISC core is in Debug Mode
Write:
0 Leave Debug Mode
1 Enter Debug Mode
Note: Freeze Mode and Software Error Interrupts have no effect on the XGDBG bit.
This bit will always read "0".
This bit will always read "0".
This bit will always read "0".
Table 10-2. XGMCTL Field Descriptions (Sheet 2 of 3)
MC9S12XE-Family Reference Manual Rev. 1.25
Description
Section 10.6, “Debug
Freescale Semiconductor
Mode”).