S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 199

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

3.3.2.5
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data are read from this register.
Write: Refer to each bit description. In emulation modes write operations will also be directed to the
external bus.
Freescale Semiconductor
Address: 0x0013 PRR
TGMRAMON
PGMIFRON
EEEIFRON
RAMHM
Reset
Field
7
5
4
3
W
R
TGMRAMON
EEE Tag RAM and FTM SCRATCH RAM visible in the memory map
Write: Anytime
This bit is used to made the EEE Tag RAM nd FTM SCRATCH RAM visible in the global memory map.
0 Not visible in the memory map.
1 Visible in the memory map.
EEE IFR visible in the memory map
Write: Anytime
This bit is used to made the IFR sector of EEE DATA FLASH visible in the global memory map.
0 Not visible in the memory map.
1 Visible in the memory map.
Program IFR visible in the memory map
Write: Anytime
This bit is used to made the IFR sector of the Program Flash visible in the global memory map.
0 Not visible in the memory map.
1 Visible in the memory map.
RAM only in higher Half of the memory map
Write: Once in normal and emulation modes and anytime in special modes
0 Accesses to $4000–$7FFF will be mapped to $14_4000-$14_7FFF in the global memory space (external
1 Accesses to $4000–$7FFF will be mapped to $0F_C000-$0F_FFFF in the global memory space (RAM area).
MMC Control Register (MMCCTL1)
0
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
access).
= Unimplemented or Reserved
0
0
6
Figure 3-10. MMC Control Register (MMCCTL1)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 3-11. MMCCTL1 Field Descriptions
EEEIFRON
0
5
;many cases assemblers are “direct page aware” and can
;automatically select direct mode.
PGMIFRON
CAUTION
0
4
Description
RAMHM
0
3
Chapter 3 Memory Mapping Control (S12XMMCV4)
EROMCTL
EROMON
2
ROMHM
0
1
ROMCTL
ROMON
0
199