S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 431

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

LDB
Operation
M[RB, #OFFS5]
M[RB, RI]
M[RB, RI]
RI-1
Loads a byte from memory into the low byte of register RD. The high byte is cleared.
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
LDB RD, (RB, #OFFS5)
LDB RD, (RS, RI)
LDB RD, (RS, RI+)
LDB RD, (RS, -RI)
—
N
1. If the same general purpose register is used as index (RI) and destination register (RD), the content of the register will not
be incremented after the data move: M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H
Not affected.
Not affected.
Not affected.
Not affected.
—
Z
—
V
Source Form
—
C
⇒ RD.L;
⇒ RD.L;
⇒ RD.L;
⇒ RI;
MC9S12XE-Family Reference Manual Rev. 1.25
$00
$00
$00
M[RS, RI] ⇒ RD.L;
Address
Mode
IDO5
IDR+
-IDR
IDR
Load Byte from Memory
⇒ RD.H
⇒ RD.H
⇒ RD.H;
0
0
0
0
(Low Byte)
1
1
1
1
0
1
1
1
0
0
0
0
RI+1 ⇒ RI;
$00 ⇒ RD.H
0
0
0
0
Machine Code
RD
RD
RD
RD
1
RB
RB
RB
RB
Chapter 10 XGATE (S12XGATEV3)
RI
RI
RI
OFFS5
LDB
0
0
1
0
1
0
Cycles
Pr
Pr
Pr
Pr
431