S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 1295

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

0x0180–0x01BF MSCAN (CAN1) Map (Sheet 2 of 2)
0x01C0–0x01FF MSCAN (CAN2) Map (Sheet 1 of 3)
Freescale Semiconductor
Address
0x01A0–
0x01B0–
Address
0x019C
0x019D
0x01AF
0x01BF
0x01C0
0x01C1
0x01C2
0x01C3
0x01C4
0x01C5
0x01C6
0x01C7
0x0196
0x0197
0x0198
0x0199
0x019A
0x019B
0x019E
0x019F
CAN1IDMR2
CAN1IDMR3
CAN1IDMR4
CAN1IDMR5
CAN1IDMR6
CAN1IDMR7
CAN1IDAR4
CAN1IDAR5
CAN1IDAR6
CAN1IDAR7
CAN1RXFG
CAN1TXFG
CAN2RFLG
CAN2BTR0
CAN2BTR1
CAN2TFLG
CAN2CTL0
CAN2CTL1
CAN2RIER
CAN2TIER
Name
Name
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
RXFRM
WUPIF
WUPIE
SAMP
CANE
SJW1
Bit 7
Bit 7
AM7
AM7
AM7
AM7
AM7
AM7
AC7
AC7
AC7
AC7
0
0
MC9S12XE-Family Reference Manual Rev. 1.25
(See
(See
CLKSRC
TSEG22
RXACT
CSCIF
CSCIE
SJW0
Bit 6
Bit 6
AM6
AM6
AM6
AM6
AM6
AM6
AC6
AC6
AC6
AC6
0
0
Detailed MSCAN Foreground Receive and Transmit Buffer
Detailed MSCAN Foreground Receive and Transmit Buffer
RSTATE1
TSEG21
RSTAT1
LOOPB
CSWAI
BRP5
Bit 5
Bit 5
AM5
AM5
AM5
AM5
AM5
AM5
AC5
AC5
AC5
AC5
FOREGROUND TRANSMIT BUFFER
0
0
FOREGROUND RECEIVE BUFFER
RSTATE0
TSEG20
RSTAT0
SYNCH
LISTEN
BRP4
Bit 4
Bit 4
AM4
AM4
AM4
AM4
AM4
AM4
AC4
AC4
AC4
AC4
0
0
TSTATE1
TSEG13
TSTAT1
BORM
BRP3
TIME
Bit 3
Bit 3
AM3
AM3
AM3
AM3
AM3
AM3
AC3
AC3
AC3
AC3
0
0
Appendix E Detailed Register Address Map
TSTATE0
TSEG12
TSTAT0
TXEIE2
WUPM
WUPE
BRP2
TXE2
Bit 2
Bit 2
AM2
AM2
AM2
AM2
AM2
AM2
AC2
AC2
AC2
AC2
TSEG11
SLPRQ
TXEIE1
SLPAK
OVRIF
OVRIE
BRP1
TXE1
Bit 1
Bit 1
AM1
AM1
AM1
AM1
AM1
AM1
AC1
AC1
AC1
AC1
Layout)
Layout)
TSEG10
INITRQ
TXEIE0
INITAK
RXFIE
BRP0
TXE0
Bit 0
AM0
AM0
AM0
AM0
AM0
AM0
Bit 0
RXF
AC0
AC0
AC0
AC0
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