S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 247

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

5.3.2.2
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data is read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
This register allows programming of two independent values determining the amount of additional stretch
cycles for external accesses (wait states).
With two bits in S12X_MMC register MMCCTL0 for every individual CSx line one of the two counter
options or the EWAIT input is selected as stretch source. The chip select outputs can also be disabled to
free up the pins for alternative functions
descriptions.
If EWAIT input usage is selected in MMCCTL0 the minimum number of stretch cycles is 2 for accesses
to the related address range.
If configured respectively, stretch cycles are added as programmed or dependent on EWAIT in normal
expanded mode and emulation expanded mode; function not available in all other operating modes.
Freescale Semiconductor
Module Base +0x000F (PRR)
Reset
W
R
External Bus Interface Control Register 1 (EBICTL1)
0
0
7
CSxE1
= Unimplemented or Reserved
Figure 5-4. External Bus Interface Control Register 1 (EBICTL1)
EXSTR12
ASIZ[4:0]
0
0
1
1
00011
10110
10111
11111
1
6
:
:
MC9S12XE-Family Reference Manual Rev. 1.25
CSxE0
Table 5-5. External Address Bus Size
EXSTR11
0
1
0
1
Table 5-6. Chip select function
1
5
(Table
CSx disabled
CSx stretched with EXSTR0
CSx stretched with EXSTR1
CSx stretched with EWAIT
Available External Address Lines
EXSTR10
5-6). Refer also to S12X_MMC section for register bit
1
4
ADDR[21:1], UDS
ADDR[22:1], UDS
ADDR[2:1], UDS
Function
:
0
0
3
Chapter 5 External Bus Interface (S12XEBIV4)
EXSTR02
1
2
EXSTR01
1
1
EXSTR00
1
0
247