S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 175

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

1. Read: Anytime.
1. Read: Anytime.
2.3.102 Port F Input Register (PTIF)
2.3.103 Port F Data Direction Register (DDRF)
Freescale Semiconductor
Address 0x0379
Address 0x037A
Write:Never, writes to this register have no effect.
Write: Anytime.
DDRF
Field
Field
PTIF
Reset
Reset
7-0
7-0
W
W
R
R
Port F input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
Port F data direction—
This register controls the data direction of pins 7 through 0.This register configures each Port F pin as either input
or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced
to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled.
The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
DDRF7
PTIF7
u
0
7
7
= Unimplemented or Reserved
DDRF6
PTIF6
u
0
6
6
Figure 2-101. Port F Data Direction Register (DDRF)
Table 2-98. DDRF Register Field Descriptions
Table 2-97. PTIF Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 2-100. Port F Input Register (PTIF)
DDRF5
PTIF5
u
0
5
5
DDRF4
PTIF4
u
0
4
4
Description
Description
u = Unaffected by reset
DDRF3
PTIF3
3
u
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
DDRF2
PTIF2
u
0
2
2
Access: User read/write
DDRF1
PTIF1
u
0
1
1
Access: User read
DDRF0
PTIF0
u
0
0
0
175
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