S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 665

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

17.3.0.3
Read: Anytime
Write: Anytime
17.3.0.4
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0002
Module Base + 0x0003
PFLT[7:0]
PCE[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PMUX7
PCE7
PIT Force Load Bits for Timer 7-0 — These bits have only an effect if the corresponding timer channel (PCE
set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding
16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will
always return zero.
PIT Enable Bits for Timer Channel 7:0 — These bits enable the PIT channels 7-0. If PCE is cleared, the PIT
channel is disabled and the corresponding flag bit in the PITTF register is cleared. When PCE is set, and if the
PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts down-
counting.
0 The corresponding PIT channel is disabled.
1 The corresponding PIT channel is enabled.
PIT Channel Enable Register (PITCE)
PIT Multiplex Register (PITMUX)
0
0
7
7
PMUX6
PCE6
0
0
6
6
Figure 17-5. PIT Channel Enable Register (PITCE)
Figure 17-6. PIT Multiplex Register (PITMUX)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 17-3. PITFLT Field Descriptions
Table 17-4. PITCE Field Descriptions
PMUX5
PCE5
0
0
5
5
PMUX4
PCE4
0
0
4
4
Description
Description
PMUX3
PCE3
0
0
3
3
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
PMUX2
PCE2
0
0
2
2
PMUX1
PCE1
0
0
1
1
PMUX0
PCE0
0
0
0
0
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