S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 369

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

10.3.1.11 XGATE Condition Code Register (XGCCR)
The XGCCR register
Module Base +0x001D
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Freescale Semiconductor
XGSEMM[7:0]
XGSEM[7:0]
Reset
Field
15–8
Field
XGN
XGV
XGC
XGZ
7–0
3
2
1
0
W
R
0
0
Semaphore Mask — These bits control the write access to the XGSEM bits.
Read:
These bits will always read "0".
Write:
0 Disable write access to the XGSEM in the same bus cycle
1 Enable write access to the XGSEM in the same bus cycle
Semaphore Bits — These bits indicate whether a semaphore is locked by the S12X_CPU. A semaphore can
be attempted to be set by writing a "1" to the XGSEM bit and to the corresponding XGSEMM bit in the same
write access. Only unlocked semaphores can be set. A semaphore can be cleared by writing a "0" to the
XGSEM bit and a "1" to the corresponding XGSEMM bit in the same write access.
Read:
0 Semaphore is unlocked or locked by the RISC core
1 Semaphore is locked by the S12X_CPU
Write:
0 Clear semaphore if it was locked by the S12X_CPU
1 Attempt to lock semaphore by the S12X_CPU
7
Sign Flag — The RISC core’s Sign flag
Zero Flag — The RISC core’s Zero flag
Overflow Flag — The RISC core’s Overflow flag
Carry Flag — The RISC core’s Carry flag
= Unimplemented or Reserved
(Figure
Figure 10-13. XGATE Condition Code Register (XGCCR)
0
0
6
10-13) provides access to the RISC core’s condition code register.
MC9S12XE-Family Reference Manual Rev. 1.25
Table 10-12. XGSEM Field Descriptions
Table 10-13. XGCCR Field Descriptions
0
0
5
0
0
4
Description
Description
XGN
0
3
XGZ
0
2
Chapter 10 XGATE (S12XGATEV3)
XGV
0
1
XGC
0
0
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