S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 469

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 11
S12XE Clocks and Reset Generator (S12XECRGV1)
11.1
This specification describes the function of the Clocks and Reset Generator (S12XECRG).
11.1.1
The main features of this block are:
Freescale Semiconductor
Revision
Number
V01.03
V01.04
V01.05
V01.06
•
•
•
•
Phase Locked Loop (IPLL) frequency multiplier with internal filter
— Reference divider
— Post divider
— Configurable internal filter (no external pin)
— Optional frequency modulation for defined jitter and reduced emission
— Automatic frequency lock detector
— Interrupt request on entry or exit from locked condition
— Self Clock Mode in absence of reference clock
System Clock Generator
— Clock Quality Check
— User selectable fast wake-up from Stop in Self-Clock Mode for power saving and immediate
— Clock switch for either Oscillator or PLL based system clocks
Computer Operating Properly (COP) watchdog timer with time-out clear window.
System Reset generation from the following possible sources:
— Power on reset
— Low voltage reset
Introduction
program execution
Features
19. Sep 2009
18. Sep 2012
20 Nov. 2008
1 Sep. 2008
Revision
Date
11.3.2.4/11-475
11.5.1/11-495
Table 11-14
Table 11-14
Sections
Affected
11.5.1
MC9S12XE-Family Reference Manual Rev. 1.25
Table 11-1. Revision History
added 100MHz example for PLL
S12XECRG Flags Register: corrected address to Module Base + 0x0003
Modified Note below
Added footnote concerning maximum clock frequencies to table
Removed redundant examples from table
Replaced reference to MMC documentation
Table 11-17./11-495
Description of Changes
469