S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 827

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

23.4.4
This functional block monitors VDD. If V
the POR is deasserted. POR asserted forces the MCU into Reset. POR Deasserted will trigger the power-
on sequence.
23.4.5
Block LVR monitors the supplies VDD, VDDX and VDDF. If one (or more) drops below it’s
corresponding assertion level, signal LVR asserts; if all VDD,VDDX and VDDF supplies are above their
corresponding deassertion levels, signal LVR deasserts. The LVR function is available only in Full
Performance Mode.
23.4.6
Subblock HTD is responsible for generating the high temperature interrupt (HTI). HTD monitors the die
temperature T
Interrupt flag HTIF is set whenever status flag HTDS changes its value.
The HTD is available in FPM and is inactive in Reduced Power Mode and Shutdown Mode.
The HT Trimming bits HTTR[3:0] can be set so that the temperature offset is zero, if accurate temperature
measurement is desired.
See
23.4.7
This part contains the register block of VREG_3V3 and further digital functionality needed to control the
operating modes. CTRL also represents the interface to the digital core logic.
23.4.8
Subblock API can generate periodical interrupts independent of the clock source of the MCU. To enable
the timer, the bit APIFE needs to be set.
The API timer is either clocked by a trimmable internal RC oscillator or the bus clock. Timer operation
will freeze when MCU clock source is selected and bus clock is turned off. See CRG specification for
details. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is
not set.
The APIR[15:0] bits determine the interrupt period. APIR[15:0] can only be written when APIFE is
cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[15:0] bits. When
the configured time has elapsed, the flag APIF is set. An interrupt, indicated by flag APIF = 1, is triggered
if interrupt enable bit APIE = 1. The timer is started automatically again after it has set APIF.
The procedure to change APICLK or APIR[15:0] is first to clear APIFE, then write to APICLK or
APIR[15:0], and afterwards set APIFE.
Freescale Semiconductor
Table 23-11
Power-On Reset (POR)
Low-Voltage Reset (LVR)
HTD - High Temperature Detect
Regulator Control (CTRL)
Autonomous Periodical Interrupt (API)
DIE
for the trimming effect of APITR.
and continuously updates the status flag HTDS.
MC9S12XE-Family Reference Manual Rev. 1.25
DD
is below V
PORD
, POR is asserted; if V
Chapter 23 Voltage Regulator (S12VREGL3V3V1)
DD
exceeds V
PORD
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