S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 220

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 3 Memory Mapping Control (S12XMMCV4)
in the memory map. This is to make sure that the correct PPAGE value will be present on stack at the time
of the RTC instruction execution.
3.5.2
Registers used for emulation purposes must be rebuilt by the in-circuit emulator hardware to achieve full
emulation of single chip mode operation. These registers are called port replacement registers (PRRs) (see
Table
aligned, word-misaligned and byte).
Each access to PRRs will be extended to 2 bus cycles for write or read accesses independent of the
operating mode. In emulation modes all write operations result in simultaneous writing to the internal
registers (peripheral access) and to the emulated registers (external access) located in the PRU in the
emulator. All read operations are performed from external registers (external access) in emulation modes.
In all other modes the read operations are performed from the internal registers (peripheral access).
Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any
PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in
emulation modes.
A summary of PRR accesses:
220
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•
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1-25). PRRs are accessible from CPU, BDM and XGATE using different access types (word
An aligned word access to a PRR will take 2 bus cycles.
A misaligned word access to a PRRs will take 4 cycles. If one of the two bytes accessed by the
misaligned word access is not a PRR, the access will take only 3 cycles.
A byte access to a PRR will take 2 cycles.
Port Replacement Registers (PRRs)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor