S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 599

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to
the IBF bit in the interrupt service routine.
15.7
15.7.1
15.7.1.1
Reset will put the IIC bus control register to its default status. Before the interface can be used to transfer
serial data, an initialization procedure must be carried out, as follows:
15.7.1.2
After completion of the initialization procedure, serial data can be transmitted by selecting the 'master
transmitter' mode. If the device is connected to a multi-master bus system, the state of the IIC bus busy bit
(IBB) must be tested to check whether the serial bus is free.
If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be sent. The data
written to the data register comprises the slave calling address and the LSB set to indicate the direction of
transfer required from the slave.
The bus free time (i.e., the time between a STOP condition and the following START condition) is built
into the hardware that generates the START cycle. Depending on the relative frequencies of the system
clock and the SCL period it may be necessary to wait until the IIC is busy after writing the calling address
to the IBDR before proceeding with the following instructions. This is illustrated in the following example.
An example of a program which generates the START signal and transmits the first byte of data (slave
address) is shown below:
Freescale Semiconductor
CHFLAG
TXSTART
IBFREE
2. Byte transfer condition (TCF bit set)
3. Address detect condition (IAAS bit set)
1. Update the frequency divider register (IBFD) and select the required division ratio to obtain SCL
2. Update the ADTYPE of IBCR2 to define the address length, 7 bits or 10 bits.
3. Update the IIC bus address register (IBAD) to define its slave address. If 10-bit address is applied
4. Set the IBEN bit of the IIC bus control register (IBCR) to enable the IIC interface system.
5. Modify the bits of the IIC bus control register (IBCR) to select master/slave mode, transmit/receive
6. If supported general call, the GCEN in IBCR2 should be asserted.
frequency from system clock.
IBCR2 should be updated to define the rest bits of address.
mode and interrupt enable or not.
Application Information
IIC Programming Examples
Initialization Sequence
Generation of START
BRSET
BSET
BRCLR
IBSR,#$20,*
IBCR,#$30
IBSR,#$20,*
MC9S12XE-Family Reference Manual Rev. 1.25
;WAIT FOR IBB FLAG TO CLEAR
;SET TRANSMIT AND MASTER MODE;i.e. GENERATE START CONDITION
;WAIT FOR IBB FLAG TO SET
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
599