S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 128

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S912XET256J2VAGR

Manufacturer Part Number
S912XET256J2VAGR
Description
16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XET256J2VAGR

Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
256 KB
Data Ram Size
16 KB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
24
Interface Type
CAN, SCI, SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V
1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.33
2.3.34
128
Address 0x024C
Address 0x024D
Write: Anytime.
Write: Anytime.
PERS
PPSS
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
Port S pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset all pull devices are enabled.
1 Pull device enabled.
0 Pull device disabled.
Port S pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin.
1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input.
0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
PERS7
PPSS7
Port S Pull Device Enable Register (PERS)
Port S Polarity Select Register (PPSS)
1
0
7
7
PERS6
PPSS6
Figure 2-31. Port S Pull Device Enable Register (PERS)
1
0
6
6
Figure 2-32. Port S Polarity Select Register (PPSS)
Table 2-30. PERS Register Field Descriptions
Table 2-31. PPSS Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
PERS5
PPSS5
1
0
5
5
PERS4
PPSS4
1
0
4
4
Description
Description
PERS3
PPSS3
3
1
3
0
PERS2
PPSS2
1
0
2
2
Access: User read/write
Access: User read/write
Freescale Semiconductor
PERS1
PPSS1
1
0
1
1
PERS0
PPSS0
1
0
0
0
(1)
(1)

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