S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 118

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

1. Read: Always reads 0x00
Chapter 2 Port Integration Module (S12XEPIMV1)
The ECLKCTL register is used to control the availability of the free-running clocks and the free-running
clock divider.
2.3.16
118
Address 0x001D (PRR)
NCLKX2
NECLK
Write: Unimplemented
DIV16
Field
EDIV
Reset
4-0
7
6
5
W
R
No ECLK—Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin.
Clock output is always active in emulation modes and if enabled in all other operating modes.
1 ECLK disabled
0 ECLK enabled
No ECLKX2—Disable ECLKX2 output
This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal Bus Clock.
Clock output is always active in emulation modes and if enabled in all other operating modes.
1 ECLKX2 disabled
0 ECLKX2 enabled
Free-running ECLK predivider—Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
Free-running ECLK Divider—Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin. Divider is always disabled in emulation
modes and active as programmed in all other operating modes.
00000 ECLK rate = Bus Clock rate
00001 ECLK rate = Bus Clock rate divided by 2
00010 ECLK rate = Bus Clock rate divided by 3, ...
11111 ECLK rate = Bus Clock rate divided by 32
PIM Reserved Register
0
0
7
= Unimplemented or Reserved
0
0
6
Table 2-16. ECLKCTL Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 2-14. PIM Reserved Register
0
0
5
0
0
4
Description
3
0
0
0
0
2
Freescale Semiconductor
0
0
1
Access: User read
0
0
0
(1)