S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 771

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Freescale Semiconductor
1. Data in SPIDRH is lost in this case.
2. SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read
1. Any write to SPIDRH or SPIDRL with SPTEF == 0 is effectively ignored.
2. Data in SPIDRH is undefined in this case.
3. SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by
XFRW Bit
XFRW Bit
of SPIDRL after reading SPISR with SPIF == 1.
writing to SPIDRL after reading SPISR with SPTEF == 1.
0
1
0
1
Read SPISR with SPTEF == 1 then
Read SPISR with SPTEF == 1
Read SPISR with SPIF == 1
Read SPISR with SPIF == 1
Table 21-10. SPTEF Interrupt Flag Clearing Sequence
Table 21-9. SPIF Interrupt Flag Clearing Sequence
MC9S12XE-Family Reference Manual Rev. 1.25
SPTEF Interrupt Flag Clearing Sequence
SPIF Interrupt Flag Clearing Sequence
then
then
then
Byte Write to SPIDRH
Byte Read SPIDRH
Word Write to (SPIDRH:SPIDRL)
Word Read (SPIDRH:SPIDRL)
Byte Write to SPIDRL
Byte Read SPIDRL
Write to SPIDRL
Chapter 21 Serial Peripheral Interface (S12SPIV5)
Read SPIDRL
1(3)
or
or
(2)
or
or
Byte Write to SPIDRL
Byte Read SPIDRL
(1)
1(2)
(1)
1
1
771