S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 143

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Freescale Semiconductor
Field
PTH
PTH
PTH
PTH
PTH
PTH
7
6
5
4
3
2
Port H general purpose input/output data—Data Register
Port H pin 7 is associated with the TXD signal of the SCI5 module and the SS signal of the routed SPI2.
The routed SPI2 function takes precedence over the SCI5 and the general purpose I/O function if the routed SPI2
module is enabled. The SCI5 function takes precedence over the general purpose I/O function if the SCI5 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port H general purpose input/output data—Data Register
Port H pin 6 is associated with the RXD signal of the SCI5 module and the SCK signal of the routed SPI2.
The routed SPI2 function takes precedence over the SCI5 and the general purpose I/O function if the routed SPI2
module is enabled. The SCI5 function takes precedence over the general purpose I/O function if the SCI5 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port H general purpose input/output data—Data Register
Port H pin 5 is associated with the TXD signal of the SCI4 module and the MOSI signal of the routed SPI2.
The routed SPI2 function takes precedence over the SCI4 and the general purpose I/O function if the routed SPI2
module is enabled. The SCI4 function takes precedence over the general purpose I/O function if the SCI4 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port H general purpose input/output data—Data Register
Port H pin 4 is associated with the RXD signal of the SCI4 module and the MISO signal of the routed SPI2.
The routed SPI2 function takes precedence over the SCI4 and the general purpose I/O function if the routed SPI2
module is enabled. The SCI4 function takes precedence over the general purpose I/O function if the SCI4 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port H general purpose input/output data—Data Register
Port H pin 3 is associated with the TXD signal of the SCI7 module and the SS signal of the routed SPI1.
The routed SPI1 function takes precedence over the SCI7 and the general purpose I/O function if the routed SPI1
module is enabled. The SCI7 function takes precedence over the general purpose I/O function if the SCI7 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port H general purpose input/output data—Data Register
Port H pin 2 is associated with the RXD signal of the SCI7 module and the SCK signal of the routed SPI1.
The routed SPI1 function takes precedence over the SCI7 and the general purpose I/O function if the routed SPI1
module is enabled. The SCI7 function takes precedence over the general purpose I/O function if the SCI7 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Table 2-49. PTH Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Description
Chapter 2 Port Integration Module (S12XEPIMV1)
143