C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 106
C8051F930-TB
Manufacturer Part Number
C8051F930-TB
Description
BOARD TARGET/PROTO W/C8051F930
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F930-TB
Contents
Board
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F930
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1472
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C8051F93x-C8051F92x
8.2.
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the data sheet associated with their corresponding sys-
tem function.
SFR Definition 8.1. DPL: Data Pointer Low Byte
SFR Page = All Pages; SFR Address = 0x82
SFR Definition 8.2. DPH: Data Pointer High Byte
SFR Page = All Pages; SFR Address = 0x83
106
Name
Reset
Name
Reset
Bit
7:0
Bit
7:0
Type
Type
Bit
Bit
DPH[7:0]
CIP-51 Register Descriptions
DPL[7:0]
Name
Name
7
0
7
0
Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed Flash memory or XRAM.
Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed Flash memory or XRAM.
6
0
6
0
5
0
5
0
Rev. 1.1
4
0
4
0
DPH[7:0]
DPL[7:0]
R/W
R/W
Function
Function
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0
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