C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 228

• Manufacturer Part Number: C8051F930-TB
• Description: BOARD TARGET/PROTO W/C8051F930
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930-TB

• Contents: Board
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F930
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1472

C8051F93x-C8051F92x
SFR Definition 21.13. P1: Port1
SFR Page = All Pages; SFR Address = 0x90; Bit-Addressable
SFR Definition 21.14. P1SKIP: Port1 Skip
SFR Page = 0x0; SFR Address = 0xD5
228
Note: Pin P1.7 is only available in 32-pin devices.
Note: Pin P1.7 is only available in 32-pin devices.
Reset
Reset
Name
Name
Type
Type
Bit
7:0
7:0
Bit
Bit
Bit
P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits.
Name
P1[7:0]
Name
7
1
7
0
Port 1 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins used
for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
1
0
6
6
Description
5
1
5
0
Rev. 1.1
4
1
4
0
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
P1SKIP[7:0]
P1[7:0]
R/W
R/W
Function
Write
3
1
3
0
2
1
2
0
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
1
1
1
0
Read
0
1
0
0