C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 142

• Manufacturer Part Number: C8051F930-TB
• Description: BOARD TARGET/PROTO W/C8051F930
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930-TB

• Contents: Board
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F930
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1472

C8051F93x-C8051F92x
SFR Definition 12.6. EIP2: Extended Interrupt Priority 2
SFR Page = All Pages; SFR Address = 0xF7
142
Reset
Name
Type
Bit
Bit
7:4
3
2
1
0
PRTC0F SmaRTClock Oscillator Fail Interrupt Priority Control.
PWARN VDD/DC+ Supply Monitor Early Warning Interrupt Priority Control.
Unused
PSPI1
Name
PMAT
R
7
0
Unused.
Read = 0000b. Write = Don’t care.
Serial Peripheral Interface (SPI1) Interrupt Priority Control.
This bit sets the priority of the SPI1 interrupt.
0: SP1 interrupt set to low priority level.
1: SPI1 interrupt set to high priority level.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
This bit sets the priority of the VDD/DC+ Supply Monitor Early Warning interrupt.
0: VDD/DC+ Supply Monitor Early Warning interrupt set to low priority level.
1: VDD/DC+ Supply Monitor Early Warning interrupt set to high priority level.
R
0
6
R
5
0
Rev. 1.1
R
4
0
Function
PSPI1
R/W
3
0
PRTC0F
R/W
2
0
PMAT
R/W
1
0
PWARN
R/W
0
0