C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 222

• Manufacturer Part Number: C8051F930-TB
• Description: BOARD TARGET/PROTO W/C8051F930
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930-TB

• Contents: Board
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F930
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1472

C8051F93x-C8051F92x
21.4. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A
software controlled value stored in the PnMAT registers specifies the expected or normal logic values of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the
software controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or
P1 input pins regardless of the XBRn settings. Note: On C8051F931/21 devices, Port Match is not
available on P1.6 or P1.7.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMAT registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(PnMAT & P0MASK) or if (P1 & P1MASK) does not equal (PnMAT & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode.
See Section “12. Interrupt Handler” on page 133 and Section “14. Power Management” on page 156 for
more details on interrupt and wake-up sources.
SFR Definition 21.4. P0MASK: Port0 Mask Register
SFR Page= 0x0; SFR Address = 0xC7
SFR Definition 21.5. P0MAT: Port0 Match Register
SFR Page= 0x0; SFR Address = 0xD7
222
Reset
Reset
Name
Name
Type
Type
7:0
7
Bit
Bit
Bit
Bit
:
0
P0MAT[7:0] Port 0 Match Value.
P0MASK[7:0] Port0 Mask Value.
Name
Name
7
0
7
1
Match comparison value used on Port 0 for bits in P0MASK which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
Selects the P0 pins to be compared with the corresponding bits in P0MAT.
0: P0.n pin pad logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin pad logic value is compared to P0MAT.n.
0
1
6
6
5
0
5
1
Rev. 1.1
P0MASK[7:0]
4
0
4
1
P0MAT[7:0]
R/W
R/W
Function
Function
3
0
3
1
2
0
2
1
1
0
1
1
0
0
0
1