C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 223

BOARD TARGET/PROTO W/C8051F930

C8051F930-TB

Manufacturer Part Number
C8051F930-TB
Description
BOARD TARGET/PROTO W/C8051F930
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F930-TB

Contents
Board
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F930
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1472
SFR Definition 21.6. P1MASK: Port1 Mask Register
SFR Page= 0x0; SFR Address = 0xBF
SFR Definition 21.7. P1MAT: Port1 Match Register
SFR Page = 0x0; SFR Address = 0xCF
Note: On C8051F931/21 devices, port match is not available on P1.6 or P1.7. The corresponding P1MASK bits
Note: On C8051F931/21 devices, port match is not available on P1.6 or P1.7.
Reset
Reset
Name
Name
Type
Type
7:0
7:0
Bit
Bit
Bit
Bit
must be set to 0b.
P1MAT[7:0] Port 1 Match Value.
P1MASK[7:0] Port 1 Mask Value.
Name
Name
7
0
7
1
Match comparison value used on Port 1 for bits in P1MASK which are set to 1.
0: P1.n pin logic value is compared with logic LOW.
1: P1.n pin logic value is compared with logic HIGH.
Selects P1 pins to be compared to the corresponding bits in P1MAT.
0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P1.n pin logic value is compared to P1MAT.n.
0
1
6
6
5
0
5
1
Rev. 1.1
P1MASK[7:0]
4
0
4
1
P1MAT[7:0]
R/W
R/W
C8051F93x-C8051F92x
Function
Function
3
0
3
1
2
0
2
1
1
0
1
1
0
0
0
1
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