C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 113
![BOARD TARGET/PROTO W/C8051F930](/photos/9/25/92560/c8051f930-tb_sml.jpg)
C8051F930-TB
Manufacturer Part Number
C8051F930-TB
Description
BOARD TARGET/PROTO W/C8051F930
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F930-TB
Contents
Board
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F930
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1472
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10. External Data Memory Interface and On-Chip XRAM
The C8051F92x-C8051F93x MCUs include on-chip RAM mapped into the external data memory space
(XRAM). 32-pin devices (C8051F930 and C8051F920) also have an External Data Memory Interface
which can be used to access off-chip memories and memory-mapped devices connected to the GPIO
ports. The external memory space may be accessed using the external move instruction (MOVX) with the
target address specified in either the data pointer (DPTR), or with the target address low byte in R0 or R1
and the target address high byte in the External Memory Interface Control Register (EMI0CN, shown in
SFR Definition 10.1).
When using the MOVX instruction to access on-chip RAM, no additional initialization is required and the
MOVX instruction execution time is as specified in the CIP-51 chapter. When using the MOVX instruction
to access off-chip RAM or memory-mapped devices, then both the Port I/O and EMIF should be configured
for communication with external devices (See Section 10.2) and MOVX instruction timing is based on the
value programmed in the External Memory Interface Timing Control Register (EMI0TC, see “External
Memory Interface Timing” on page 118).
Important Note: MOVX write operations can be configured to target Flash memory, instead of XRAM. See
Section “13. Flash Memory” on page 145 for more details. The MOVX instruction accesses XRAM by
default.
10.1. Accessing XRAM
The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms,
both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit
register which contains the effective address of the XRAM location to be read from or written to. The
second method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM
address. Examples of both of these methods are given below.
10.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the
DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the
accumulator A:
The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
10.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits
of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the
effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
MOV
MOVX
MOV
MOV
MOVX
DPTR, #1234h
A, @DPTR
EMI0CN, #12h
R0, #34h
a, @R0
; load DPTR with 16-bit address to read (0x1234)
; load contents of 0x1234 into accumulator A
; load high byte of address into EMI0CN
; load low byte of address into R0 (or R1)
; load contents of 0x1234 into accumulator A
Rev. 1.1
C8051F93x-C8051F92x
113
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