C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 212

• Manufacturer Part Number: C8051F930-TB
• Description: BOARD TARGET/PROTO W/C8051F930
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930-TB

• Contents: Board
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F930
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1472

C8051F93x-C8051F92x
21. Port Input/Output
Digital and analog resources are available through 24 I/O pins (C8051F930/20) or 16 I/O pins
(C8051F931/21). Port pins are organized as three byte-wide ports. Port pins P0.0–P2.6 can be defined as
digital or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as
general purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P2.7 can be used
as GPIO and is shared with the C2 Interface Data signal (C2D). See Section “27. C2 Interface” on
page 319 for more details.
The designer has complete control over which digital and analog functions are assigned to individual port
pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. See Section 21.3 for more information on the Crossbar.
All Port I/Os are 5 V tolerant when used as digital inputs or open-drain outputs. For Port I/Os configured as
push-pull outputs, current is sourced from the VDD/DC+ supply. Port I/Os used for analog functions can
operate up to the VDD/DC+ supply voltage. See Section 21.1 for more information on Port I/O operating
modes and the electrical specifications chapter for detailed electrical specifications.
212
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
SMBus
T0, T1
UART
P0
P1
P2
SPI0
SPI1
PCA
CP0
CP1
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
Figure 21.1. Port I/O Functional Block Diagram
2
4
2
4
7
2
8
8
8
Rev. 1.1
XBR2, PnSKIP
XBR0, XBR1,
Crossbar
Decoder
Registers
Priority
Digital
(ADC0, CP0, and CP1 inputs,
To EMIF
To Analog Peripherals
VREF, IREF0, AGND)
8
8
8
P0MASK, P0MAT
P1MASK, P1MAT
Port Match
Cells
Cells
Cell
P0
I/O
P1
I/O
P2
I/O
External Interrupts
PnMDIN Registers
EX0 and EX1
PnMDOUT,
P1.7–2.6 only available
P2.7 is available on all
on 32-pin devices
devices
P0.0
P0.7
P1.0
P1.6
P1.7
P2.0
P2.6
P2.7