C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 294

• Manufacturer Part Number: C8051F930-TB
• Description: BOARD TARGET/PROTO W/C8051F930
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930-TB

• Contents: Board
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F930
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1472

C8051F93x-C8051F92x
25.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR2CN.3) defines
the Timer 3 operation mode. Timer 3 can also be used in Capture Mode to measure the external oscillator
source or the Comparator 1 period with respect to another oscillator. The ability to measure the
Comparator 1 period with respect to the system clock is makes using Touch Sense Switches very easy.
Timer 3 may be clocked by the system clock, the system clock divided by 12, external oscillator source
divided by 8, or Comparator 1 output. The external oscillator source divided by 8 and Comparator 1 output
is synchronized with the system clock.
25.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, external oscillator clock source divided by 8, or Comparator 1
output. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in
the Timer 3 reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in
Figure 25.7, and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled
(if EIE1.7 is set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts
are enabled and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8
bits (TMR3L) overflow from 0xFF to 0x00.
294
External Clock / 8
Comparator 1
SYSCLK / 12
T3XCLK[1:0]
00
01
11
SYSCLK
Figure 25.7. Timer 3 16-Bit Mode Block Diagram
M
T
H
3
M
T
3
L
0
1
CKCON
M
T
H
2
M
T
2
L
TR3
M
T
1
M
T
0
S
C
A
1
S
C
A
0
TCLK
Rev. 1.1
TMR3RLL TMR3RLH
TMR3L
TMR3H
Reload
To ADC
T3XCLK1
T3XCLK0
TF3CEN
T3SPLIT
TF3LEN
TF3H
TF3L
TR3
Interrupt